Curriculum Vitae

Arnab Ardhendu Purkayastha, Ph.D.

Assistant Professor of Electrical & Computer Engineering · Western New England University
OfficeSleith Hall 209, Western New England University
ProfilesGitHub · LinkedIn
Profile

Professional Summary

Assistant Professor and engineering researcher working at the intersection of FPGA-based acceleration, high-performance computing, and embedded systems. An engineering educator committed to hands-on, entrepreneurially minded learning. Active in the Kern Entrepreneurial Engineering Network (KEEN) as a participant, presenter, workshop leader, and faculty mentor. Guides undergraduates to peer-reviewed publications and award-winning design projects.

FPGA and reconfigurable computingHigh-performance and cloud computingHardware acceleration for machine learning at the edgeVLSI design and physical-design optimizationEntrepreneurially minded, project-based engineering education
Education

Degrees

2021

Ph.D., Electrical & Computer Engineering

University of North Carolina at Charlotte, NC, USA
Dissertation: Empowering Reconfigurable Platforms for Massively Parallel Applications
2013

M.Tech., Microelectronics & VLSI

National Institute of Technology (NIT) Agartala, India
2011

B.E., Electrical Engineering

Tripura University, India
Experience

Academic & Professional Appointments

Jan 2022 – Present

Assistant Professor, Electrical & Computer Engineering

Western New England University, Springfield, MA
  • Undergraduate and graduate teaching in computer engineering and first-year engineering; first-year advisor; senior capstone advisor; undergraduate research mentor.
Aug 2021 – Dec 2021

Research Scientist

TeCSAR Labs, UNC Charlotte, NC
  • High-performance computing applications on cloud and edge FPGAs.
2017 – 2021

Graduate Research Assistant

UNC Charlotte, NC
  • Ph.D. research on FPGA parallelism, memory-access optimization, and OpenCL high-level synthesis, including three industry-funded projects.
2017 – 2021

Graduate Teaching Assistant

UNC Charlotte, NC
  • Computer Architecture, Heterogeneous Computing, Network Theory I, Programming in C++, and Logic Design for undergraduate and graduate students.
Feb 2014 – Jan 2017

Assistant Professor

MU, Mumbai, India
  • Taught VLSI Design, IC Technology, and Microcontrollers.
Aug 2013 – Jan 2014

Instrumentation Engineer

Mass-Weigh Systems Pvt. Ltd., Mumbai, India
  • PLC programming and HMI interfaces for industrial weighing and control systems.
Publications

Peer-Reviewed Work

Journal Articles

  1. 1.
    A. A. Purkayastha, J. Tharwani, S. Aggarwal, “Ant Colony Optimization for CMOS Physical Design: Reducing Layout Area and Improving Aspect Ratio in VLSI Circuits,” Electronics (MDPI), vol. 14, no. 24, art. 4825, 2025. doi:10.3390/electronics14244825
  2. 2.
    J. Tharwani, A. A. Purkayastha, “Cost-Performance Evaluation of General Compute Instances: AWS, Azure, GCP, and OCI,” International Journal of Computer Trends and Technology, vol. 72, no. 11, pp. 248–255, 2024.
  3. 3.
    A. Danesh Pazho, G. Alinezhad Noghre, A. A. Purkayastha, J. Vempati, O. Martin, H. Tabkhi, “A Survey of Graph-Based Deep Learning for Anomaly Detection in Distributed Systems,” IEEE Transactions on Knowledge and Data Engineering, vol. 36, pp. 1–20, 2023. doi:10.1109/TKDE.2023.3282898
    Google Scholar Metrics: #1 venue in Databases & Information Systems (h5-index 126).
  4. 4.
    “Current Mirror Using FinFETs,” International Journal for Research in Applied Science & Engineering Technology (IJRASET), 2021.
  5. 5.
    A. A. Purkayastha, S. Rogers, S. A. Shiddibhavi, H. Tabkhi, “LLVM-Based Automation of Memory Decoupling for OpenCL Applications on FPGAs,” Microprocessors and Microsystems (Elsevier), vol. 72, art. 102909, 2020. doi:10.1016/j.micpro.2019.102909
    Google Scholar Metrics: #6 venue in Computer Hardware Design (h5-index 60).
  6. 6.
    “Improving Performance of VLSI Circuits Using Different Modes of FinFET,” International Journal of Research and Analytical Reviews (IJRAR), 2019.

Conference Papers

  1. 7.
    C. Burnham*, A. A. Purkayastha, N. Magotra, “Speculative Backpropagation AI Training Framework for FPGA-Oriented Implementation at the IoT Edge,” 69th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2026.
  2. 8.
    J. Tharwani, S. Aggarwal, A. A. Purkayastha, “Quantifying Virtualization Overhead for CPU-Intensive HPC Workloads in Hypervisors: A Comparative Study of KVM, Proxmox VE, Xen, and Hyper-V,” IEEE SoutheastCon, pp. 1–6, 2026. doi:10.1109/SoutheastCon63549.2026.11476478
  3. 9.
    A. A. Purkayastha, S. Aggarwal, J. Tharwani, “Heuristic-Driven Resource Optimization for Decoupled Memory Channels on FPGAs,” IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), vol. 4, pp. 1–6, 2026. doi:10.1109/IATMSI68868.2026.11465435
  4. 10.
    S. Aggarwal, A. A. Purkayastha, J. Tharwani, “Empowering IoT with Federated Learning: A Cross-Domain Survey from Healthcare to Industry,” IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), vol. 4, pp. 1–5, 2026.
  5. 11.
    S. Centeno*, C. Sprague*, A. A. Purkayastha, R. Simar, N. Magotra, “Exploring Parallelism in FPGA-Based Accelerators for Machine Learning Applications,” 68th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 842–846, 2025. doi:10.1109/MWSCAS53549.2025.11244519
  6. 12.
    A. A. Purkayastha, J. Tharwani, S. Aggarwal, “FPGA or GPU? Analyzing Comparative Research for Application-Specific Guidance,” IEEE SoutheastCon, Concord, NC, pp. 1258–1263, 2025. doi:10.1109/SoutheastCon56624.2025.10971274
  7. 13.
    J. Tharwani, S. Aggarwal, A. A. Purkayastha, “Evaluating HPC-Style CPU Performance and Cost in Virtualized Cloud Infrastructures,” IEEE SoutheastCon, Concord, NC, pp. 1239–1244, 2025. doi:10.1109/SoutheastCon56624.2025.10971705
  8. 14.
    J. Ekong, A. A. Purkayastha, G. Ekong, “Work in Progress: Impact of Collaborative Learning Strategies on Anxiety Reduction in Introductory Programming Courses,” ASEE Annual Conference & Exposition, 2024.
  9. 15.
    S. Centeno*, A. A. Purkayastha, “Beyond Trial and Error: Automating Delay Generation in Assembly with Algorithmically Calculated For-Loops,” Global Interdisciplinary Green Cities Conference, 2024.
  10. 16.
    S. Aggarwal, A. A. Purkayastha, “SecureTrack: A Contact Tracing IoT Platform for Monitoring Infectious Diseases,” Global Interdisciplinary Green Cities Conference, 2023.
  11. 17.
    A. A. Purkayastha, H. Tabkhi, “Design Study on Impact of Memory Access Parallelism for Cloud FPGAs,” 34th IEEE International System-on-Chip Conference (SOCC), pp. 254–259, 2021. doi:10.1109/SOCC52499.2021.9739477
  12. 18.
    J. Thiagarajan, A. A. Purkayastha, A. Patil, H. Tabkhi, “Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs,” 33rd IEEE International System-on-Chip Conference (SOCC), pp. 213–218, 2020. doi:10.1109/SOCC49529.2020.9524765
  13. 19.
    A. A. Purkayastha, S. Raghavendran, J. Thiagarajan, H. Tabkhi, “Exploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs,” IEEE High Performance Extreme Computing Conference (HPEC), pp. 1–7, 2019. doi:10.1109/HPEC.2019.8916236
  14. 20.
    A. A. Purkayastha, S. A. Shiddhibhavi, H. Tabkhi, “Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications,” 31st IEEE International System-on-Chip Conference (SOCC), pp. 55–60, 2018. doi:10.1109/SOCC.2018.8618501

Teaching Scholarship

  1. 21.
    A. A. Purkayastha, “Remote-Controlled Deep Work Sign: AI-Enhanced Product Design,” KEEN Engineering Unleashed, Card #6116, 2026.

Book

  1. 22.
    “VLSI Design,” Tech-Neo Publications, ISBN 978-93-90376-04-9, 2020.

* Undergraduate student mentee.

Research

Research Projects & Outcomes

Industry fundedIEEE TKDE 2023

Anomaly Detection in Complex Distributed Systems

Graph Isomorphism Networks to find and mitigate malicious software processes and gadget chains when hardware/software components of a large system are updated.

IEEE SOCC 2021

Memory Access Parallelism for Cloud FPGAs

Formalized Double Data Rate and burst-transfer optimization to cut global-memory latency on Xilinx cloud FPGAs.

Industry fundedIEEE SOCC 2020

Automating Parallelism on Cloud FPGAs

A generic template and Python-based tool for OpenCL design-space exploration on FPGAs.

Elsevier MICPRO 2020

LLVM-Based Memory Decoupling on FPGAs

An LLVM automation tool that decouples memory access from computation on Intel Stratix V FPGAs: over 2× speedup and over 40% energy reduction on Rodinia benchmarks.

Industry fundedIEEE HPEC 2019

OpenCL Pipes on Cloud FPGAs

Evaluated memory-access decoupling with OpenCL pipes on Xilinx cloud FPGA benchmark applications.

IEEE SOCC 2018

Taxonomy of Parallelism on FPGAs

A taxonomy formalizing how OpenCL temporal and spatial parallelism map onto FPGAs.

Funding

Grants

KEEN Faculty Development Workshop Grant (Co-PI)
“Transform Teaching with EM and Technology – Make Learning Fun Again!”
$12,5002025
Davis Educational Foundation Grant (Co-PI)
“Effect of Pedagogical Interventions on Student Motivations and Attitudes in Quantitative Courses”
$11,5002024
Rice University & Octavo Systems
FPGA hardware for the Ghost-in-Machine research collaboration
$2,5002025
WNE Summer Research Grants (2×)
ENGR 103 Arduino curriculum redesign
$5,0002023, 2024
WNE Honors Course Creation Grant
LaTeX for technical writing with Overleaf
$1,200
Total$32,700

Proposals Submitted

Teaching

Courses Taught

Western New England University: Undergraduate

CPE 310Microprocessors I
CISC-to-RISC microprocessor systems; revamped with new material in 2023–24.
Fall 2022 – Fall 2025
CPE 360Microprocessors II
Redesigned in 2025 around the ATmega328PB: firmware-centric labs on interrupts, peripherals, and device drivers; AMD industry guest lecture.
Spring 2022 – Spring 2025
ENGR 103Introduction to Engineering
Arduino curriculum redesign (2023–24) and a Raspberry Pi Pico 2 W robotics platform for ResQTech-themed design challenges and Botbash.
Fall 2022 – Fall 2025
ENGR 105Computer Programming for Engineers
MATLAB; redesigned with Write-Pair-Share, pair programming, and vertical non-permanent surfaces (Davis project).
Spring 2022 – Spring 2025
ENGR 110Data Acquisition and Processing
New preparation: LabVIEW and Raspberry Pi Pico data acquisition with an original AI-enhanced product-design module.
Spring 2026
CPE 491/591Special Topics: VLSI Design
Full physical-design flow (partitioning to routing, SRAM) with DSCH/Microwind labs and an algorithm-implementation project.
Spring 2024, Spring 2025

Western New England University: Graduate

CPE 691Special Topics: VLSI Design
New course created; later cross-listed as CPE 491/591.
Spring 2023
Engineering Education

Engineering Education & Pedagogy

Kern Entrepreneurial Engineering Network (KEEN), 2022 – Present

2022ICE 1.0 STEM Faculty Teaching Workshop (6 days), Denver, CO — participant
2023KEEN STEM Faculty Training Conference (3 days), Atlanta, GA — participant
2024ICE 2.0 Workshop (6 days), Phoenix, AZ — participant and presenter
2025KEEN National Conference, Austin, TX — participant
2025Co-organized and led a 3-day KEEN faculty-development workshop at WNE for new College of Engineering faculty; led the Arduino experiential-learning session and mentored participants as they implemented course innovations
2025KEEN Leader Meeting, Milwaukee, WI — participant

Pedagogical Development & Teaching Innovation

Mentoring

Student Research & Design Mentoring

WNE Jet Engine ECU

Lucian Dupont-LeBlanc · Senior capstone · 2025–26
First Prize, Best Senior Design Project in ECE (2026)
  • Controls and engine-control-unit architecture for a cross-departmental capstone with Mechanical Engineering and Pratt & Whitney.

Speculative Backpropagation for FPGA-Based Edge AI

Cameron Burnham · Senior capstone · 2025–26
IEEE MWSCAS 2026
  • Reusable benchmarking platform for speculative backpropagation on FPGA targets.

Parallelism in FPGA-Based ML Accelerators

Sed Centeno & Christopher Sprague · Senior capstone · 2024–25
IEEE MWSCAS 2025
  • Rice University Ghost-in-Machine collaboration: ~15% faster neural-network training on an Octavo Systems FPGA board.

Car Theft Alarm System

Logan Paranto · Senior capstone · 2023–24
  • Battery-powered intrusion detector using a pressure sensor, buzzer alarm, and real-time GPS location on an ESP32 microcontroller.

IoT-Controlled Desk for Immersive Tabletop Gaming

Corbin Veitch & Tim Fortune · Senior capstone · 2023–24
  • Home Assistant–based desk controlling lights and sound over MQTT from a single embedded processor, with custom Python libraries and UIs.

Botbash First-Year Robotics Competition

ENGR 103 student teams
First place (2025); third place (2024); second place (2023)
  • Advised first-year teams designing robots for ResQTech disaster-response challenges on the Pico 2 W platform.
Talks

Invited Talks

Invited research presentation: FPGA-based memory-channel optimization and resource-efficient computing architectures

ABV-Indian Institute of Information Technology and Management (ABV-IIITM), Gwalior, India (virtual), 2026

“Accelerators & AI: Optimizing Energy for a Sustainable Future”

AICTE Training and Learning (ATAL) Academy Faculty Development Program on Energy, Sustainability and Climate Change, India (online), Jan 16–22, 2025

“Electronics Systems: Devices, IC and Applications”

AICTE Short-Term Training Program, Department of ECE, NIT Arunachal Pradesh, India, Mar 14–18, 2022
Service

Professional Service

Conference Leadership

Journal Reviewer

  • IEEE Transactions on Neural Networks and Learning Systems (2)
  • IEEE Transactions on Circuits and Systems
  • Microprocessors and Microsystems (Elsevier)
  • The Journal of Supercomputing (Springer, 3)
  • Scientific Reports (Springer Nature)
  • Artificial Intelligence Review (Springer)
  • Journal of Intelligent Information Systems (Springer)
  • Circuits, Systems, and Signal Processing (Springer)
  • Silicon (Springer)
  • Journal of Low Power Electronics (ASP, 2)

Conference & Other Reviewing

  • IEEE MWSCAS 2025 (3 papers) and 2026
  • IEEE ISIE 2025
  • Int'l Conference on VLSI Design & Embedded Systems 2024 (4 papers)
  • Global Interdisciplinary Green Cities Conference 2024
  • External Ph.D. dissertation reviewer, Vignan University, India

University & Community

Recognition

Awards & Honors

Expertise

Technical Skills

AI & machine learningFPGA acceleration of neural-network training; graph neural networks; federated learning; generative-AI–assisted engineering workflows (code development, technical writing, course design) and teaching students to use AI critically
ProgrammingC++, OpenCL, CUDA, MATLAB, Python
Hardware descriptionVerilog, VHDL
Hardware platformsIntel/Altera Stratix V and Arria 10 FPGAs; Xilinx Alveo and Virtex-5 FPGAs; AMD FirePro W7100 GPU; Raspberry Pi Pico 2 W; ATmega328PB; Arduino
CloudAWS EC2 F1 (Xilinx VU9P), NSF Chameleon Cloud FPGAs
ToolsXilinx Vivado, Vitis and ISE; Intel HLS; Cadence Virtuoso; ModelSim; OrCAD PSpice; DSCH; Microwind; Tanner; LabVIEW; Keil µVision
Operating systemsLinux (Ubuntu, CentOS), Windows